Due to the increase of the number of I/Os in modern electronic products, the packaging technology has evolved from the early Plug-In method to the more advanced Surface Mounting Technology (SMT) in order to meet the new demands. There are two representative SMT packages, the Dual-In-Line Package (DIP), by Fairchild, and Flat Package (FP), by Texas Instrument Institute. Another packaging method drawing much attention is the Ball Grid Array (BGA), which uses protruding poles arranged in an array to replace the pins of conventional Pin Grid Array (PGA). PGA is a through hole packaging technology that is restricted by the pitch between the separate areas on the printed board. On the other hand, BGA is a surface packaging technology without such restriction. Thus, BGA is suitable for packaging compact products with high density of I/Os. With the emergence of Flip Chip used in high-level products, BGA is becoming the technology of choice in the modern packaging industry. However, in practice, when applying Flip Chip Ball Grid Array (FCBGA) on Flip Chip Substrate, the current BGA technology suffers from the problems of crowed routing space, substrate warpage, and the solder resist too thick to be adhered to the IC devices. It is necessary to develop a different packaging structure and method for solving the aforementioned problems.
As shown in FIG. 1A, a conventional Flip Chip Substrate includes 4 to 8 layers of printed circuit boards. The substrate could be made of ceramic or organic material. The communication between the layers of boards is through the tiny holes drilled mechanically or with laser. Wires are extended through the tiny holes and made into bump pads for connecting the IC bumps. The conventional approach usually requires a larger space; hence, restricts the density and the flexibility of routing. It is desirable to device a technology to fill the tiny laser-drilled holes with plating copper in order to form the communication between the layers of boards. This will improve the density and the flexibility of routing.
In the IC packaging process, the substrates are treated with a high temperature step which could sometimes deform the substrates. The deformed substrates, warped or twisted, are difficult for the IC chips to be adhered on. To avoid heat deformation, the present invention provides a Fine Pitch flip chip substrate with a mesh pattern to increase the stiffness of the substrates. The mesh pattern improves the resistance to heat deformation.
In a conventional IC packaging process, the flip chip substrate is coated with a photo solder resist made of Epoxy to prevent short-circuit of the tin bridge due to the flowing of melted soldering tin during the solder reflow. Also, a bump pad is formed at the area for connecting each solder bump of I/O on the IC chips in the packaging process. This step is difficult for the flip chip substrate that requires its alignment precision to be within 25 μm. Meanwhile, the thickness of the solder resist is usually controlled between 15 to 45 μm during manufacturing. Therefore, the bump pads buried in the solder resist will degrade the connection between the IC bumps and the pads on the substrate.